OMB No . 0704 - 0188

Rule based inference has demonstrated its applicability for a wide variety of domains. As users have grown more ~omfort­ able with this technology, the scope of attempted proJects has grown from small laboratory demonstrations into massive real world time-critical systems. However, as the scope of systems has increased, execution speed has become u~acceptabl~. <?ne method of improving inference performance IS parallehzatwn. The parallelization of inference is n?t as s~ightforw~d as ~he parallelization of traditional numenc algonthms. Difficulties stem from the unpredictability _of exe~ution paths, ~mall absol_ute task sizes, wide relative task Size vanances, and high proportion of shared volatile data. This paper describes the completed and ongoing efforts of the Parallel Inferencing Performance Evaluation and Refinement project1 (PIP~R) . PIPER Phase I p~oduced an initial parallil inference engme (expert system tool kit) for the BBN Butterfly< l Plus. Currently, PIPER Phase II is investigating parallel inference techniques on Thinking Machines' Connection Machine (CM) parallel computer. The Phase I inference engine is based on the Merit Enhanced Traversal Engine (METE) algorithm which is an extension of Forgy's (1979) RETE algorithm. To evaluate the efficacy of this design and implementation, an iterating 108 rule knowledge base was composed. This rule set was designed to roughly simulate ~he inform~tion rich nat~r~ ~f its target application domam, Strategic Defense Imtiative contact discrimination, and was processed on from 7 to 85 Butterfly(R) Plus processor nodes. Three uniprocessor control groups were also employed to gauge speed-up. ,Using the control group which produced the most conservative speed-up factors, the Phase I inference engine achieved a maximum true speed-up in excess of 29 utilizing. This speed-up was attributed to: (I) parallelism in constant tests and two input node tests, as well as (2) pipelining between (a) two input node tests and conflict resolution, and (b) test processing and overhead corresponding to the parallel implementation.